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    Each process has a page table that maintains a mapping of virtual pages to physical pages.A page table is a software construct managed by operating system that is kept in main memory.When a logical address is generated by the CPU, its page number is presented to the TLB.If the page number is found its frame number is immediately available and is used to access memory.The page table contains the base address of each page in physical memory.The base address is combined with the page offset to define the physical memory address that is sent to the memory unit.

    Paging is a memory-management scheme that permits the physical address space of a process to be non-contiguous.In this note, we explain a) the background for used of TLB hardware, b) current solutions for maintaining TLB coherence and c) finally a proposal for a unified cache-TLB coherence protocol (that is hardware based).In this section we introduce the basic terminology and the set-up where TLBs are used.For a process, a pointer to the page table (Page-Table Base Register-PTBR) is stored in a register.Changing page table requires changing only this one register, substantially reducing the context-switch time.

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